Shift register circuit, display device, and method for driving shift register circuit

ABSTRACT

Provided is a shift register circuit which includes: first through N-th circuit sections ( 1   a   , 1   b ) (N is an integer equal to or larger than 2) in each of which a plurality of shift register stages (SR 1 , SR 2 , . . . , SRn) are connected in cascade; and supply wires ( 10   b   , 10   c   , 10   e   , 10   f ). Each of the first through N-th circuit sections ( 1   a   , 1   b ) receives drive signals (CKA 1 , CKA 2 , CKB 1 , CKB 2 ) for driving the shift register stages (SR 1 , SR 2 , . . . , SRn) via supply wires ( 10   b   , 10   c   , 10   e   , 10   f ) exclusive for the each of the first through N-th circuit sections ( 1   a   , 1   b ).

TECHNICAL FIELD

The present invention relates to a shift register circuit that ismonolithically built into a display panel.

BACKGROUND ART

In recent years, the fabrication of a monolithic gate driver has beendeveloped for the purpose of cost reduction. The monolithic gate driveris such a gate driver that is formed from amorphous silicon on a liquidcrystal panel. The term “monolithic gate driver” is also associated withthe terms such as “gate driver-free”, “built-in gate driver in panel”,and “gate in panel”.

FIG. 13 illustrates an exemplary configuration of a shift registercircuit 100 constituting a monolithic gate driver.

The shift register circuit 100 has stages (shift register stages) SRk (kis a natural number which satisfies 1≦k≦n). Each of the stages SRkincludes a set terminal SET, an output terminal GOUT, a reset terminalRESET, a Low power supply input terminal VSS, and clock input terminalsCLK1 and CLK2. To the set terminal SET of each of the stages SRk (k≧2),an output signal Gk−1 of a preceding stage SRk−1 is supplied. To the setterminal SET of the initial stage SR1, a gate start pulse signal GSP issupplied. The output terminal GOUT of each of the stages SRk (k≧1)supplies an output signal Gk to a corresponding scanning signal linedisposed in an active region 101. To the reset terminal RESET of each ofthe stages SRk (k≦n−1), an output signal Gk+1 of a succeeding stageSRk+1 is supplied. To the reset terminal RESET of the final stage SRn, aclear signal CLR is supplied.

To the Low power supply input terminal VSS, a Low power supply voltageVSS, which is a low-electric-potential-side power supply voltage in eachstage SRk, is supplied. To one of the clock input terminal CLK1 and theclock terminal CLK2, a clock signal CKA1 is supplied, and to the otherone of the clock input terminal CLK1 and the clock terminal CLK2, aclock signal CKA2 is supplied. Such clock signals supplied to the clockinput terminal CLK1 and the clock input terminal CLK2 are reversedbetween adjacent stages.

The clock signals CKA1 and CKA2 have such complementary phases thattheir active clock pulses (here, high level periods) do not overlap eachother, as illustrated in FIG. 14. A High level side (active side)voltage of the clock signals CKA1 and CKA2 is VGH, and a Low level side(non-active side) voltage of the clock signals CKA1 and CKA2 is VGL. TheLow power supply voltage VSS is equal to the Low level side voltage VGLof the clock signals CKA1 and CKA2. In this example, the clock signalCKA1 and the clock signal CKA2 are in reverse phases, but it is alsopossible that an active clock pulse period of one of the clock signalCKA1 and the clock signal CKA2 is encompassed within a non-active periodof the other one (i.e., a clock duty is less than ½).

The gate start pulse signal GSP is a signal which becomes active in afirst clock pulse period of 1 frame period (1F). The clear signal CLR isa signal which becomes active (here, High) in a final clock pulse periodof 1 frame period (1F).

FIG. 15 illustrates an exemplary configuration of each of the stages SRkof the shift register circuit 100 of FIG. 13.

Each of the stages SRk includes five transistors T1, T2, T3, T4, and T5,and a capacitor C1. These transistors are all n-channel type TFTs.

As to the transistor T1, a gate and a drain are connected to a setterminal SET, and a source is connected to a gate of the transistor T5.As to the transistor T5, which is an output transistor of each of thestages SRk, a drain is connected to the clock input terminal CLK1, and asource is connected to the output terminal GOUT. That is, the transistorT5 serves as a transmission gate for allowing/blocking passage of aclock signal to be supplied to the clock input terminal CLK1. Thecapacitor C1 is connected between the gate and the source of thetransistor T5. A node connected to the gate of the transistor T5 isreferred to as netA.

As to the transistor T3, a gate is connected to the reset terminalRESET, a drain is connected to the node netA, and a source is connectedto the Low power supply input terminal VSS. As to the transistor T4, agate is connected to the reset terminal RESET, a drain is connected tothe output terminal GOUT, and a source is connected to the Low powersupply input terminal VSS.

As to the transistor T2, a gate is connected to the clock terminal CLK2,a drain is connected to the output terminal GOUT, and a source isconnected to the Low power supply input terminal VSS.

Next, the following describes an operation of each of the stages SRkwith reference to FIG. 16.

In 1 frame period, first, the gate start pulse signal GSP is supplied,as a shift pulse of the shift register circuit 100, to the set terminalSET of the initial stage SR1. In the shift register circuit 100, thisshift pulse is transferred sequentially through the stages SRk connectedin cascade, so that an active pulse of an output signal Gk is output.

In each of the stages SRk, until the shift pulse is supplied to the setterminal SET, the transistors T4 and T5 are in a high impedance state,and the transistor T2 turns on every time a clock signal supplied fromthe clock input terminal CLK2 becomes a High level. Accordingly, theoutput terminal GOUT maintains Low.

When the shift pulse is supplied to the set terminal SET, the stage SRkenters a period in which it generates a gate pulse which is an activepulse of the output signal Gk, and the transistor T1 turns on. Thiscauses the capacitor C1 to be charged. The charging of the capacitor C1increases an electric potential of the node netA to VGH-Vth (VGHrepresents a High level of the gate pulse and Vth is a threshold voltageof the transistor T1). As a result, the transistor T5 turns on, and theclock signal supplied from the clock input terminal CLK1 appears in thesource of the transistor T5. Since the electric potential of the nodenetA rapidly increases due to a bootstrap effect of the capacitor C1 atthe instant when a clock pulse (High level) is input to the clock inputterminal CLK1, the transistor T5 achieves a large overdrive voltage.Consequently, almost all amplitude of VGH of the clock pulse supplied tothe clock input terminal CLK1 is transmitted to the output terminal GOUTof the stage SRk, and is then output as a gate pulse.

After the input of the shift pulse to the set terminal SET is finished,the transistor T1 turns off. Then, in order to release charge retentioncaused by floating of the node netA and the output terminal GOUT of thestage SRk, a gate pulse of a succeeding stage SRk+1 is supplied as areset pulse to the reset terminal RESET. This causes the transistors T3and T4 to turn on. Accordingly, the node netA and the output terminalGOUT are connected to the Low power supply voltage VSS. Consequently,the transistor T5 turns off. After input of the reset pulse is finished,the period in which the stage SRk generates the gate pulse ends, and aperiod in which the output terminal GOUT maintains Low starts again.

In this way, gate pulses of output signals Gk are sequentially suppliedto respective gate lines, as illustrated in FIG. 17.

Such a shift register circuit utilizing a monolithic gate drivertechnique is described also in Patent Literature 1, etc.

CITATION LIST Patent Literature 1

-   Japanese Patent Application Publication, Tokukai, No. 2005-50502 A    (Publication Date: Feb. 24, 2005)

SUMMARY OF INVENTION Technical Problem

However, as display devices have larger sizes and higher resolution,capacitances of cross capacitors formed between signal wires for drivinga display panel and a load connected to an output of a shift registerstage SRk are increasing. In a case where all loads connected to a powersupply which generates a gate pulse are low loads, the gate pulse has ashape close to a rectangle, as illustrated in (a) of FIG. 18. Theincrease in the number of cross capacitors and load causes wiring delay,leading to deformation of a waveform of the gate pulse, as illustratedin (b) of FIG. 18. The deformation of the waveform of the gate pulsecauses a reduction of a High period, a deviation of an operation timingof a picture element TFT, etc. In order to solve this problem, it isnecessary to secure a sufficient High period of the gate pulse and anaccurate pulse timing by taking measures such as (i) increasing a size(channel width W/channel length L) of a transistor used in the shiftregister circuit 100 and (ii) supplying, instead of a gate pulse 105,which should originally be used, a gate pulse 106 having a largeramplitude (see (c) of FIG. 18).

Such a load on a power supply which generates a gate pulse is describedbelow.

As illustrated in FIG. 13, as wires for signals driving the shiftregister circuit 100, a plurality of wires such as a wire 100 a for thegate start pulse signal GSP, a wire 100 b for the clock signal CKA1, awire 100 c for the clock signal CKA2, a wire 100 d for the Low powersupply voltage VSS, and a wire 100 e for the clear signal CLR areprovided on the display panel.

Among these wires 100 a through 100 e, the wires 100 b through 100 deach have (i) a main wire that is drawn out from a corresponding powersupply or signal source so that it reaches the vicinity of the shiftregister stages SRk and (ii) branch wires that are drawn out from themain wire to the respective shift register stages SRk. FIG. 13illustrates, as an example, a main wire 100 b(1) and branch wires 100b(2) of the wire 100 b and a main wire 100 c(1) and branch wires 100c(2) of the wire 100 c.

Since the wires 100 b and 100 c each having the main wire and branchwires intersect with another wire, a cross capacitor is formed betweenthe wires. The same is true for the other wires. Further, each of thewires 100 b and 100 c has its wire capacitance, too. Especially, thenumber of parts where the cross capacitor is formed increases inproportion to an increase in the number of rows of picture elementswhich occurs as a panel has higher resolution. Further, in a case whereeach row of picture elements is constituted by picture elements of asingle color, picture element rows for respective colors are necessary.This causes a great increase in the number of rows, thereby leading to aremarkable increase in the number of parts where the cross capacitor isformed.

Each of the wires 100 b and 100 c is connected to a shift register stageSRk via a clock input terminal CLK1, and when the shift register stageSRk output a gate pulse, each of the wires 100 b and 100 c is connectedto a corresponding gate line GLk. That is, a clock supply is a powersupply which generates a gate pulse, and the wire capacitor and thecross capacitor of the wires 100 b and 100 c become loads on the powersupply which generates a gate pulse.

FIG. 19 illustrates an equivalent circuit of each pixel PIX in theactive region 101 of FIG. 13.

Each pixel PIX is provided corresponding to an intersection of a gateline GLk and a source line SLj (j is a natural number). The pixel PIXincludes a TFT110, which is a selection element, a liquid crystalcapacitor Clc, and a retention capacitor Ccs. A gate of the TFT110 isconnected to the gate line GLk, a source of the TFT110 is connected tothe source line SLj, and a drain 110 d of the TFT110 is connected to apicture element electrode 111. The liquid crystal capacitor Clc isconstituted by the picture element electrode 111, a common electrodeCOM, and a liquid crystal layer sandwiched between the picture elementelectrode 111 and the common electrode COM. The retention capacitor Ccsis constituted by the drain 111 d, a retention capacitor line CSL, andan insulating film sandwiched between the drain 111 d and the retentioncapacitor line CSL.

The gate line GLk is connected to the output terminal GOUT of each ofthe shift register stages SRk. As is clear from FIG. 15, the gate lineGLk is connected to the clock supply via the clock signal CKA1 or CKA2of FIG. 13 during a period in which the transistor T5 is on. That is,the gate line GLk becomes a load of the clock supply. Further, the gateline GLk is connected to a power supply of the Low power supply voltageVSS at the time of reset of the shift register stage SRk. That is, thegate line GLk becomes a load of the power supply of the Low power supplyvoltage VSS.

Further, a cross capacitor Csgx is formed at an intersection of the gateline GLk and the source line SLj. To the cross capacitor Csgx, theliquid crystal capacitor Clc and the retention capacitor Ccs areconnected during a period in which the TFT 110 is on. That is, the crosscapacitor Csgx, the liquid crystal capacitor Clc, and the retentioncapacitor Ccs become loads of the clock supply and power supply of theLow power supply voltage VSS. Such capacitors which become loads of theclock supply and power supply of the Low power supply voltage VSSinclude the cross capacitors Csgx, the liquid crystal capacitors Clc,and the retention capacitors Ccs of all of the picture elements PIXconnected to the source line SLj.

Further, to the gate line GLk, a gate-to-source capacitor Cgs and agate-to-drain capacitor Cgd, each of which is a parasitic capacitor ofthe TFT 110, is connected. The gate-to-drain capacitor Cgd includes aparasitic capacitor formed between the gate line GLk and the pictureelement electrode 111. That is, the gate-to-source capacitor Cgs and thegate-to-drain capacitor Cgd become loads of the clock supply and thepower supply of the Low power supply voltage VSS.

Such loads illustrated in FIG. 19 are loads within a display region.

Next, FIG. 20 illustrates how the wires 100 b and 100 c for the clocksignals CKA1 and CKA2 and the transistors in the shift register stageSRk are connected.

The wires 100 b and 100 c are connected to the clock input terminals CKAand CKB, for example, in the case of the shift register stage SRkconfigured as illustrated in FIG. 15. Accordingly, to the wires 100 band 100 c, parasitic capacitors 115, 116, 117, and 118 which aregate-to-source capacitors and gate-to-drain capacitors of thetransistors T2 and T5 are connected.

Since all of such load capacitors are connected to the power supplywhich generates a gate pulse, deformation of a waveform of the gatepulse becomes quite large. In a case where a High period of the gatepulse becomes short due to the increase of the waveform deformation, itis impossible to secure a period for sufficiently charging the liquidcrystal capacitor Clc. This hinders achievement of higher resolutiondisplay. Accordingly, in a case where a size of a transistor isincreased in order to improve the waveform deformation, the transistorsize becomes very large since an output transistor represented by thetransistor T5 originally has a very large channel width so as to have alarge electric current supply capability. The monolithic gate drivertechnique requires an especially large size since an element (especiallyamorphous silicon) of small carrier mobility is used. This is contraryto a trend towards a reduction in frame width of a display panel.Further, a large-sized element has high possibility of occurrence of aproduction defect in any part of the element. This hinders achievementof high panel production yield.

Further, in a case where the amplitude of the clock signals CKA1 andCKA2 is increased in order to supply the gate pulse 106 with a largeamplitude as illustrated in (c) of FIG. 18, it is necessary to increasea clock power supply voltage. This is contrary to the trend towards areduction in power supply voltage for lower power consumption and higheroperation speed.

In view of such circumstances, possible realistic measures againstdeformation of a waveform of a gate pulse are limited to an insufficientincrease in transistor size which allows only a minimum electric currentsupply capability and an insufficient increase in power supply voltagefor suppressing power consumption to a minimum. The former method,however, reduces a margin of the electric current supply capability ofthe transistor, thereby lowering a upper limit of a load that can bedriven. The latter method leaves no sufficient margin for the powersupply voltage which generates a gate pulse to drive a transistor.

As described above, a conventional shift register circuit has a problemthat a sufficient operation margin cannot be secured.

The present invention was attained in view of the above problems, and anobject of the present invention is to provide a shift register circuitwhich makes it possible to secure a sufficient operation margin, adisplay device including the shift register circuit, and a method fordriving the shift register circuit.

Solution to Problem

A shift register circuit of the present invention includes: firstthrough N-th circuit sections (N is an integer equal to or larger than2) in each of which a plurality of shift register stages are connectedin cascade; and supply wires, each of the first through N-th circuitsections receiving a drive signal for driving the plurality of shiftregister stages via a supply wire exclusive for said each of the firstthrough N-th circuit sections out of the supply wires.

According to the invention, the number of intersections of each of thesupply wires for supplying a drive signal and another wire greatlydeclines. This makes it possible to greatly reduce the number of crosscapacitors per supply wire for supplying a drive signal. Further, thenumber of shift register stages connected to each of the supply wiresfor supplying a drive signal greatly declines. This allows a greatreduction in sum of parasitic capacitors in connection parts with theshift register stages. Accordingly, a drive signal that is supplied froma drive signal source to each of the supply wires for supplying a drivesignal can have a waveform with smaller deformation, and therefore awaveform of an output signal from each of the shift register stages canhave a waveform with smaller deformation, as compared with aconventional art. Consequently, it is possible to increase a chargingratio of a load without increasing a voltage range of the drive signalsource nor increasing a transistor size (channel width), therebyincreasing an operation margin of the shift register stages.

It is thus possible to provide a shift register circuit that makes itpossible to secure a sufficient operation margin.

A method of the present invention for driving a shift register circuitwhich includes first through N-th circuit sections (N is an integerequal to or larger than 2) in each of which a plurality of shiftregister stages are connected in cascade, includes the step ofsupplying, to each of the first through N-th circuit sections, a drivesignal for driving the plurality of shift register stages via a supplywire exclusive for said each of the first through N-th circuit sections.

According to the invention, it is possible to provide a method fordriving a shift register circuit that makes it possible to secure asufficient operation margin.

Advantageous Effects of Invention

A shift register circuit of the present invention includes: firstthrough N-th circuit sections (N is an integer equal to or larger than2) in each of which a plurality of shift register stages are connectedin cascade; and supply wires, each of the first through N-th circuitsections receiving a drive signal for driving the plurality of shiftregister stages via a supply wire exclusive for said each of the firstthrough N-th circuit sections out of the supply wires.

It is thus possible to provide a shift register circuit that makes itpossible to secure a sufficient operation margin.

A method of the present invention for driving a shift register circuitwhich includes first through N-th circuit sections (N is an integerequal to or larger than 2) in each of which a plurality of shiftregister stages are connected in cascade, includes the step ofsupplying, to each of the first through N-th circuit sections, a drivesignal for driving the plurality of shift register stages via a supplywire exclusive for said each of the first through N-th circuit sections.

It is thus possible to provide a method for driving a shift registercircuit that makes it possible to secure a sufficient operation margin.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates an embodiment of the present invention, and is ablock diagram illustrating a configuration of a shift register circuitof Example 1.

FIG. 2 is a timing chart explaining signals of the shift registercircuit of FIG. 1.

FIG. 3 illustrates an embodiment of the present invention, and is ablock diagram illustrating a configuration of a shift register circuitof Example 2.

FIG. 4 is a timing chart explaining signals of the shift registercircuit of FIG. 3.

FIG. 5 illustrates an embodiment of the present invention, and is ablock diagram illustrating a configuration of a shift register circuitof Example 3.

FIG. 6 is a timing chart explaining signals of the shift registercircuit of FIG. 5.

FIG. 7 illustrates an embodiment of the present invention, and is ablock diagram illustrating a configuration of a shift register circuitof Example 4.

FIG. 8 is a timing chart explaining signals of the shift registercircuit of FIG. 7.

FIG. 9 illustrates an embodiment of the present invention, and is ablock diagram illustrating a configuration of a shift register circuitof Example 5.

FIG. 10 is a timing chart explaining signals of the shift registercircuit of FIG. 9.

FIG. 11 illustrates an embodiment of the present invention, and is ablock diagram illustrating a configuration of a display device.

FIG. 12 illustrates an embodiment of the present invention, and is adiagram explaining a gate scan direction and a data signal supplydirection of the display device. (a) through (c) of FIG. 12 are diagramsillustrating variations of the supply direction.

FIG. 13 illustrates a conventional art, and is a block diagramillustrating a configuration of a shift register.

FIG. 14 is a timing chart explaining signals of the shift registercircuit of FIG. 13.

FIG. 15 is a circuit diagram illustrating a configuration of a shiftregister stage of FIG. 13.

FIG. 16 is a timing chart illustrating an operation of the shiftregister stage of FIG. 15.

FIG. 17 is a timing chart illustrating an operation of the shiftregister circuit of FIG. 13.

FIG. 18 illustrates a conventional art, and is a waveform diagramexplaining waveform deformation. (a) of FIG. 18 is a waveform diagramillustrating a waveform with small deformation, (b) of FIG. 18 is awaveform diagram illustrating a waveform with large deformation, and (c)of FIG. 18 is a waveform diagram illustrating a waveform with improveddeformation.

FIG. 19 illustrates a conventional art, and is a circuit diagramexplaining parasitic capacitors formed around a picture element.

FIG. 20 illustrates a conventional art, and is a circuit diagramexplaining a parasitic capacitor in a part in which a supply wire forsupplying a drive signal and a shift register stage are connected toeach other.

DESCRIPTION OF EMBODIMENTS

An embodiment of the present invention is described below with referenceto FIGS. 1 through 12.

FIG. 11 illustrates a configuration of a liquid crystal display device11 which is a display device of the present embodiment.

The liquid crystal display device 11 includes a display panel 12, aflexible printed circuit board 13, and a control board 14.

The display panel 12 is an active matrix display panel arranged suchthat, using TFTs produced with the use of amorphous silicon, an activeregion (display region) 12 a, a plurality of gate lines (scanning signallines) GL, a plurality of source lines (data signal lines) SL, and agate driver (scanning signal line driving circuit) 15 are built onto aglass substrate. The display panel 12 may be produced with the use ofTFTs formed from polycrystalline silicon, CG silicon, microcrystallinesilicon, amorphous oxide semiconductor (e.g., IGZO), or the like. Theactive region 12 a is a region where a plurality of picture elements PIXare arranged in a matrix manner. Each of the picture elements PIXincludes a TFT 21 that is a selection element of the picture element, aliquid crystal capacitor CL, and an auxiliary capacitor Cs. A gate ofthe TFT 21 is connected to the gate line GL, and a source of the TFT 21is connected to the source line SL. The liquid crystal capacitor CL andauxiliary capacitor Cs are connected to a drain of the TFT 21.

The plurality of gate lines GL are gate lines GL1, GL2, GL3, . . . andGLn which are connected to respective outputs of the gate driver(scanning signal line driving circuit) 15. The plurality of source linesSL are source lines SL1, SL2, SL3, . . . SLm, which are connected torespective outputs of a source driver 16 that will be described later.Although not shown, an auxiliary capacitor wire is formed to apply anauxiliary capacitor voltage to each of the auxiliary capacitors Cs ofthe picture elements PIX.

The gate driver 15 is provided in one of two regions adjoining theactive region 12 a of the display panel 12 in a direction in which thegate lines GL extend, and sequentially supplies a gate pulse (scanpulse) to each of the gate lines GL with the use of a shift registercircuit provided therein. Another gate driver may be provided in theother region adjoining the active region 12 a of the display panel 12 inthe direction in which the gate lines GL extend, and scans gate lines GLdifferent from those scanned by the gate driver 15. These gate driversare formed from at least one of amorphous silicon, polycrystallinesilicon, CG silicon, microcrystalline silicon, and amorphous oxidesemiconductor (e.g., IGZO: In—Ga—Zn—O) and built into the display panel12 so as to be monolithically fabricated with the active region 12 a.Examples of the gate driver 15 can include all gate drivers referred towith the terms such as “monolithic gate driver”, “gate driver-free”,“built-in gate driver in panel”, and “gate in panel”.

The flexible printed circuit board 13 includes the source driver 16. Thesource driver 16 supplies a data signal to each of the source lines SL.The control board 14 is connected to the flexible printed circuit board13 and supplies necessary signals and power to the gate driver 15 andthe source driver 16. The signals and power to be supplied to the gatedriver 15 from the control board 14 pass through the flexible printedcircuit board 13 and are then supplied to the gate driver 15 on thedisplay panel 12.

A region outside the active region 12 a on the display panel 12 is aframe region 12 b. The gate driver 15 is provided in the frame region 12b, and the flexible printed circuit board 13 is connected to the frameregion 12 b.

Such an arrangement in which a gate driver is fabricated by themonolithic gate driver technique like the gate driver 15 is suitable fora case where all picture elements PIX in a single row are pictureelements of an identical color and where the gate driver 15 drives thegate lines GL on a color (R, G, or B) basis. In this case, it isunnecessary to prepare the source driver 16 for each of the colors. Thisis advantageous since a size of the source driver 16 and a size of theflexible printed circuit board 13 can be reduced.

Next, the following describes a configuration of a shift registercircuit provided in the gate driver 15 of the liquid crystal displaydevice 11 configured as above, with reference to Examples. Note thateach stage (shift register stage) SRk of the shift register circuitdescribed below is not limited to a specific configuration, and can be,for example, the circuit illustrated in FIG. 15, and therefore theconfiguration of each stage (shift register stage) SRk of the shiftregister circuit is not described.

Example 1

FIG. 1 illustrates a configuration of a shift register circuit 1 of thepresent example.

The shift register circuit 1 includes a first circuit section 1 a, asecond circuit section 1 b, and wires 10 a, 10 b, 10 c, 10 d, 10 e, 10f, 10 g, and 10 h.

The first circuit section 1 a is arranged such that stages (shiftregister stages) SRk (k is a natural number which satisfies 1≦k≦m) areconnected in cascade. Each of the stages SRk includes a set terminalSET, an output terminal GOUT, a reset terminal RESET, a Low power supplyinput terminal VSS, and clock input terminals CLK1 and CLK2. To the setterminal SET of each of the stages SRk (k≧2), an output signal Gk−1 froma preceding stage SRk−1 is supplied. To the set terminal SET of theinitial stage SR1 of the first circuit section 1 a, a gate start pulsesignal GSP1 is supplied. In each of the stages SRk (1≦k≦m), the outputterminal GOUT supplies an output signal Gk to a corresponding gate lineGLk provided in the active region 12 a. To the reset terminal RESET ofeach of the stages SRk (k≦m−1), an output signal Gk+1 of a succeedingstage SRk+1 is supplied. To the reset terminal RESET of the final stageSRm of the first circuit section 1 a, a clear signal CLR1 is supplied.

To the Low power supply input terminal VSS, a Low power supply voltageVSS, which is a low-electric-potential-side power supply voltage in eachstage SRk, is supplied. To one of the clock input terminal CLK1 and theclock terminal CLK2, a clock signal CKA1 is supplied, and to the otherone of the clock input terminal CLK1 and the clock terminal CLK2, aclock signal CKA2 is supplied. Such clock signals supplied to the clockinput terminal CLK1 and the clock input terminal CLK2 are reversedbetween adjacent stages.

The clock signals CKA1 and CKA2 have such complementary phases thattheir active clock pulse periods (here, high level periods) do notoverlap each other, as illustrated in FIG. 2. A High level side (activeside) voltage of the clock signals CKA1 and CKA2 is VGH, and a Low levelside (non-active side) voltage of the clock signals CKA1 and CKA2 isVGL. The Low power supply voltage VSS is equal to the Low level sidevoltage VGL of the clock signals CKA1 and CKA2. In this example, theclock signal CKA1 and the clock signal CKA2 are in reverse phases, butit is also possible that an active clock pulse period of one of theclock signal CKA1 and the clock signal CKA2 is encompassed within anon-active period of the other one (i.e., a clock duty is less than ½).

The gate start pulse signal GSP1 is a signal which becomes active in afirst clock pulse period of 1 frame period (1F), i.e., a period t1described below. The clear signal CLR1 is a signal which becomes active(here, High) twice in 1 frame period (1F) so as to reset the finalstages of the first circuit section 1 a and the second circuit section 1b.

The second circuit section 1 b is arranged such that stages (shiftregister stages) SRk (k is a natural number which satisfies m+1≦k≦n) areconnected in cascade. Each of the stages SRk includes a set terminalSET, an output terminal GOUT, a reset terminal RESET, a Low power supplyinput terminal VSS, and clock input terminals CLK1 and CLK2. To the setterminal SET of each of the stages SRk (m+2≦k≦n), an output signal Gk−1of a preceding stage SRk−1 is supplied. To the set terminal SET of theinitial stage SR1 of the second circuit section 1 b, a gate start pulsesignal GSP2 is supplied. In each of the stages SRk (m+1≦k≦n), the outputterminal GOUT supplies an output signal Gk to a corresponding gate lineGLk provided in the active region 12 a. To the reset terminal RESET ofeach of the stages SRk (m+1≦k≦n−1), an output signal Gk+1 of asucceeding stage SRk+1 is supplied. To the reset terminal RESET of thefinal stage SRm of the second circuit section 1 b, a clear signal CLR1is supplied.

To the Low power supply input terminal VSS, the Low power supply voltageVSS is supplied. To one of the clock input terminal CLK1 and the clockterminal CLK2, a clock signal CKB1 is supplied, and to the other one ofthe clock input terminal CLK1 and the clock terminal CLK2, a clocksignal CKB2 is supplied. Such clock signals supplied to the clock inputterminal CLK1 and the clock input terminal CLK2 are reversed betweenadjacent stages.

The clock signals CKB1 and CKB2 have such complementary phases thattheir active clock pulse periods (here, high level periods) do notoverlap each other, as illustrated in FIG. 2. A High level side (activeside) voltage of the clock signals CKB1 and CKB2 is VGH, and a Low levelside (non-active side) voltage of the clock signals CKB1 and CKB2 isVGL. In this example, the clock signal CKB1 is in an identical phase tothe clock signal CKA1, and the clock signal CKB2 is in an identicalphase to the clock signal CKA2. The Low power supply voltage VSS isequal to the Low level side voltage VGL of the clock signals CKB1 andCKB2. In this example, the clock signal CKB1 and the clock signal CKB2are in reverse phases, but it is also possible that an active clockpulse period of one of the clock signal CKB1 and the clock signal CKB2is encompassed within a non-active period of the other one (i.e., aclock duty is less than ½).

The gate start pulse signal GSP2 is a signal which becomes active in afirst clock pulse period of a period t2, in 1 frame period (1F), whichfollows the period t1 for scanning in the first circuit section 1 a. Theclear signal CLR1 is identical to that described in the explanation ofthe first circuit section 1 a.

In a case where a direction along a shift direction of a shift pulse ineach of the first circuit section 1 a and the second circuit section 1 bis referred to as a direction (first direction) D, the first circuitsection 1 a and the second circuit section 1 b are aligned in thedirection D in the frame region 12 b.

On the frame region 12 b, a plurality of wires are formed such as thewire 10 a for the gate start pulse signal GSP1, the wire 10 b for theclock signal CKA1, the wire 10 c for the clock signal CKA2, the wire 10d for the Low power supply voltage VSS, the wire 10 e for the clocksignal CKB1, the wire 10 f for the clock signal CKB2, the wire 10 g forthe gate start pulse signal GSP2, and the wire 10 h for the clear signalCLR1.

Among these wires 10 a through 10 g, the wires 10 b through 10 f eachhave (i) a main wire that is drawn out from a corresponding power supplyor signal source so that it reaches the vicinity of the shift registerstages SRk and (ii) branch wires that are drawn out from the main wireto the respective shift register stages SRk. FIG. 1 illustrates, asexamples, a main wire 10 b(1) and branch wires 10 b(2) of the wire 10 b,a main wire 10 c(1) and branch wires 10 c(2) of the wire 10 c, a mainwire 10 e(1) and branch wires 10 e(2) of the wire 10 e, and a main wire10 f(1) and branch wires 10 f(2) of the wire 10 f.

In a case where a direction perpendicular to the direction D on asurface on which the circuit is formed is referred to as a direction(second direction) E, the wires 10 b and 10 c that respectivelycorrespond to supply wires for the clock signals (drive signals) CKA1and CKA2 which supply wires are exclusive for the first circuit section1 a, and the wires 10 e and 10 f that respectively correspond to supplywires for the clock signals CKB1 and CKB2 which supply wires areexclusive for the second circuit section 1 b are provided in a region(first region) 12 b(1) that is located on an E1 side (predetermined sideof the second direction) which is one side of the direction E for bothof the first circuit section 1 a and the second circuit section 1 b soas to extend from a D1 side (a predetermined side of the firstdirection) which is one side of the direction D towards a correspondingone of the first circuit section 1 a and the second circuit section 1 b.

In this example, the E1 side corresponds to an outer side of the displaypanel 12. Note, however, that the predetermined side of the seconddirection may be any one of the two sides of the direction E (e.g., thepredetermined side of the second direction may be an E2 side that is anopposite side to the E1 side in a case where the shift register circuit1 is not on board in the display device). In this example, the D1 sidecorresponds to a side where a clock signal source which is a drivesignal source is present. Note, however, that, generally, thepredetermined side of the first direction may be any one of the twosides of the direction D.

In this example, all of the wires 10 a through 10 h are drawn out froman outside of the display panel 12, as described with reference to FIG.11. In this case, the wires 10 a through 10 h extend from the D1 side ofthe direction D in which the shift register circuit 1 is formed towardsrespective connection parts with the shift register circuit 1 (see, forexample, the wires 10 a through 10 g illustrated in FIG. 1).

In this case, in a case where the wires 10 b and 10 c connected to thefirst circuit section 1 a are disposed in an outer side of the displaypanel 12 than the wires 10 e and 10 f connected to the second circuitsection 1 b as illustrated in FIG. 1, there is no intersection of thewires 10 b and 10 c and the wires 10 e and 10 f. This arrangementcorresponds to an arrangement in which a main wire of a supply wirecorresponding to an i-th circuit section (i=1, 2) that is farther awayfrom the D1 side when the shift register circuit 1 is viewed in thedirection D is disposed closer to the E1 side of the region 12 b(1).This reduces the number of intersections of the wires 10 b, 10 c, 10 e,and 10 f and another wire which occur since each of the wires 10 b, 10c, 10 e, and 10 f which is constituted by a main wire and branch wiresis connected to a corresponding shift register stage SRk, as comparedwith the case of the wires 100 b and 100 c of FIG. 13. In a case wherem=(½)n, the number of intersections becomes ½.

The arrangement of the present example allows a great reduction in thenumber of intersections of the wires 10 b, 10 c, 10 e, and 10 f andanother wire, as described above. This makes it possible to greatlyreduce the number of cross capacitors per supply wire for supplying adrive signal. Further, the number of shift register stages SRk connectedto a single supply wire for supplying a drive signal greatly declines.This greatly reduces a sum of parasitic capacitors in connection partswith the shift register stages SRk illustrated in FIG. 20. Accordingly,a drive signal (here, a clock signal) supplied from a clock supply to asupply wire for supplying the drive signal can have a waveform withsmaller deformation, and therefore an output signal of a shift registerstage SRk can have a waveform with smaller deformation, as compared witha conventional art, as illustrated in (a) of FIG. 18. It is thereforepossible to sufficiently secure a selection period of a picture elementPIX and increase a charging ratio without increasing a voltage range ofa clock supply nor increasing a transistor size (channel width). Thisallows an increase in operation margin of the shift register stages SRkaccordingly.

It is thus possible to provide a shift register circuit which makes itpossible to secure a sufficient operation margin, a display deviceincluding the shift register circuit, and a method for driving the shiftregister circuit.

FIG. 2 illustrates an operation of the shift register circuit 1configured as above.

It is assumed here that m=(½)n is satisfied. The period t1 is a formerhalf of 1 frame period (1F), and the period t2 is a latter half of 1frame period (1F). The clear signal CLR1 becomes active in a final clockpulse period of the period t1 and in a final clock pulse period of theperiod t2.

Accordingly, as shown by (1) in FIG. 1, throughout 1 frame period (1F),the gate scan is carried out first in the first circuit section 1 a in adirection from the D2 side towards the D1 side, and is then carried outin the second circuit section 1 b in a direction from the D2 sidetowards the D1 side. In this case, a data signal from the source driver16 can be supplied in a single direction, i.e., a direction from the D2towards the D1 side as shown by (2) in FIG. 1 (or a direction from theD1 side towards the D2 side) or can be supplied in two directions, i.e.,a direction from the D2 side towards the D1 side and a direction fromthe D1 side towards the D2 side as shown by (3) in FIG. 1.

The above description has dealt with an example in which the drivesignal is a clock signal. However, the drive signal is not limited tothis. The drive signal may be a drive signal for a shift register stageSRk which drive signal does not have a uniform periodicity.

The above description has dealt with an example in which the shiftregister circuit 1 is constituted by the first and second circuitsections. However, the present example is not limited to this. The shiftregister circuit 1 may be a shift register circuit that includes firstthrough N-th circuit sections (N is an integer equal to or larger than2) in each of which a plurality of shift register stages are connectedin cascade. In a case where a direction along the shift direction isreferred to as a first direction and a direction perpendicular to thefirst direction on a surface on which the circuit is formed is referredto as a second direction, the shift register circuit includes the firstthrough N-th circuit sections so that the first through N-th circuitsections are aligned in the first direction. In each of the firstthrough N-th circuit sections, the shift register stages are driven by adrive signal supplied by a supply wire exclusive for each of the firstthrough N-th circuit sections. The number of shift register stages isdetermined for each of the first through N-th circuit sections. Thesupply wire for supplying a drive signal is provided for each of thefirst through N-th circuit sections. Alternatively, further, the supplywire for supplying a drive signal is disposed in a first region that islocated closer, than a corresponding one of the first through N-thcircuit sections, to a predetermined side of the second direction, whichis one side of the second direction and which is common to all of thefirst through N-th circuit sections, so as to extend from apredetermined side of the first direction, which is one side of thefirst direction and which is common to all of the first through N-thcircuit sections, towards a corresponding one of the first through N-thcircuit sections.

Further, in the above example, drive signal sources are provided only inone side (e.g., D2 side). However, the present example is not limited tothis. The drive signal sources may be provided both in the D1 side andthe D2 side. In this case, in a case where (i) a drive signal supplywire corresponding to an i-th circuit section (i is an integer whichsatisfies 1≦i≦N) that is closer to the D1 side (the predetermined sideof the first direction) than the D2 side (the opposite side to thepredetermined side of the first direction) is disposed so as to extendfrom the D1 side and (ii) a drive signal supply wire corresponding to ani-th circuit section that is closer to the D2 side than the D1 side isdisposed so as to extend from the D2 side, a balance is achieved betweenthe lengths of the supply wires on the D1 side of the shift registercircuit 1 and the lengths of the supply wires on the D2 side of theshift register circuit 1. Accordingly, a difference is unlikely to occurin deformation of a waveform of a drive signal, and therefore adifference is unlikely to occur in deformation of a waveform of anoutput signal of a shift register stage SRk.

That is, such an arrangement is possible in which (i) a drive signalsupply wire corresponding to an i-th circuit section that is providedcloser to the predetermined side of the first direction which is oneside of the first direction is disposed so as to extend from thepredetermined side of the first direction towards the corresponding i-thcircuit section and (ii) a drive signal supply wire corresponding to ani-th circuit section that is provided closer to the opposite side to thepredetermined side of the first direction is disposed so as to extendfrom the opposite side to the predetermined side of the first directiontowards the corresponding i-th circuit section.

Example 2

FIG. 3 illustrates a configuration of a shift register circuit 1 of thepresent example.

The shift register circuit 1 of FIG. 3 has an identical configuration tothe shift register circuit 1 of FIG. 1. However, clock signals (drivesignals) CKA12, CKA22, CKB12, and CKB22, gate start pulse signals GSP12and GSP22, and a clear signal CLR2 are input instead of the clocksignals CKA1, CKA2, CKB1, and CKB2, the gate start pulse signals GSP1and GSP2, and the clear signal CLR1 of FIG. 1, respectively.

As illustrated in FIG. 4, the clock signals CKA12, CKA22, CKB12, andCKB22 have the same duty ratio as the clock signals CKA1, CKA2, CKB1,and CKB2 and have a cycle that is two times longer than that of theclock signals CKA1, CKA2, CKB1, and CKB2. The gate start pulse signalsGSP1 and GSP2 become active in an initial clock pulse period of 1 frameperiod (1F). The clear signal CLR2 becomes active in a final clock pulseperiod of 1 frame period (1F).

This makes it possible to perform scan simultaneously in the firstcircuit section 1 a and the second circuit section 1 b, as shown by (1)of FIG. 3. The gate scan may be performed in a direction from the D2side towards the D1 side both in the first circuit section 1 a and thesecond circuit section 1 b or may be performed in a direction from theD2 side towards the D1 side in the first circuit section 1 a and in adirection from the D1 side towards the D2 side in the second circuitsection 1 b. In a case where the gate scan is performed in a directionfrom the D1 side towards the D2 side in the second circuit section 1 b,in FIG. 3, the gate start pulse signal GSP22 is supplied to the shiftregister stage SRn of the second circuit section 1 b in a manner reverseto the order of cascade connection, instead of supplying the gate startpulse signal GSP22 to the shift register stage SRm+1 which is theinitial stage of the second circuit section 1 b. In this way, a shiftpulse is shifted from the D1 side towards the D2 side. In this case, theclear signal CLR2 is supplied to a reset terminal RESET of the shiftregister stage SRm+1 of the second circuit section 1 b.

In a case where such gate scan is performed, a data signal is suppliedfrom the source driver 16 in a direction from the D2 side towards the D1side in the first circuit section 1 a and in a direction from the D1side towards the D2 side in the second circuit section 1 b, as shown by(2) of FIG. 3.

That is, of a screen which is divided into an upper screen and a lowerscreen, the first circuit section 1 a drives the upper screen and thesecond circuit section 1 b drives the lower screen. This corresponds tothe configuration of (c) of FIG. 12 that is described later.

According to the arrangement of the present example, a cycle of a clocksignal is long, and a screen is divided into upper and lower screenswhich are respectively driven by first through N-th circuit sectionsindependently allocated to the upper and lower screens. This makes itpossible to secure a long selection period of a picture element PIX.Accordingly, the arrangement of the present example is suitableespecially for high resolution and high-speed display.

Example 3

FIG. 5 illustrates a configuration of a shift register circuit 1 of thepresent example.

The shift register circuit 1 of FIG. 5 has an identical configuration tothe shift register circuit 1 of FIG. 1. However, clock signals (drivesignals) CKA13, CKA23, CKB13, and CKB23, and a clear signal CLR3 areinput instead of the clock signals CKA1, CKA2, CKB1, and CKB2, and theclear signal CLR1 of FIG. 1, respectively.

As illustrated in FIG. 6, the clock signal CKA13 and CKA23 are signalsobtained by replacing the period t2 of the clock signals CKA1 and CKA2with a rest period in which a non-active level is maintained. The clocksignals CKB13 and CKB23 are signals obtained by replacing the period t1of the clock signals CKB1 and CKB2 with a rest period in which anon-active level is maintained. The clear signal CLR3 is a signal whichbecomes an active level only in a final clock pulse period of 1 frameperiod (1F).

As shown by (1) of FIG. 6, the gate scan is performed in a directionfrom the D2 side towards the D1 side in the period t1 and performed inthe direction from the D2 side towards the D1 side in the period t2.

As described above, in the present example, a drive signal of onecircuit section has a rest period within an operation period of anothercircuit section. The clock signals CKA13 and CKA23 charge/discharge thewires 10 b and 10 c only in the period t1 which is an operation periodof the first circuit section 1 a, and the clock signals CKB13 and CKB23charge/discharge the wires 10 e and 10 f only in the period t2 which isan operation period of the second circuit section 1 b. Accordingly, thepresence of the rest period reduces a loss of electricity associatedwith charging/discharging of the supply wires for supplying a drivesignal, thereby further reducing waveform deformation. Further, areduction in power consumption can also be achieved since an operationof a corresponding i-th circuit section is stopped in the rest period.

Example 4

FIG. 7 illustrates a configuration of a shift register circuit 2 of thepresent example.

The shift register circuit 2 of FIG. 7 includes a first circuit section2 a and a second circuit section 2 b.

The first circuit section 2 a is different from the first circuitsection 1 a of FIG. 1 in that an output signal Gm+1 of a shift registerstage SRm+1 which is an initial stage of the second circuit section 2 bis supplied, instead of the clear signal CLR, to a reset terminal RESETof a shift register stage SRm which is the final stage of the firstcircuit section 2 a. The second circuit section 2 b is different fromthe second circuit section 1 b of FIG. 1 in that (i) an output signal Gmof a shift register stage SRm is supplied, instead of the gate startpulse signal GSP2, to a set terminal SET of a shift register stage SRm+1which is an initial stage of the second circuit section 2 b and (ii) theoutput signal Gm+1 of the shift register stage SRm+1 which is theinitial stage of the second circuit section 2 b is supplied to the resetterminal RESET of the shift register stage SRm as described above.

To a set terminal SET of a shift register stage SR1 which is an initialstage of the first circuit section 2 a, a gate start pulse signal GSP3that is identical to the gate start pulse signal GSP1 is supplied.Further, instead of the clock signals CKA1, CKA2, CKB1, and CKB2, andthe clear signal CLR of FIG. 1, clock signals (drive signals) CKA13,CKA23, CKB13, and CKB23, and the clear signal CLR3 are input in thisorder.

As illustrated in FIG. 8, the clock signals CKA13 and CKA23 are signalsobtained by replacing the period t2 of the clock signals CKA1 and CKA2with a rest period in which a non-active level is maintained. The clocksignals CKB13 and CKB23 are signals obtained by replacing the period t1of the clock signals CKB1 and CKB2 with a rest period in which anon-active level is maintained. The clear signal CLR3 is a signal whichbecomes an active level only in a final clock pulse period of 1 frameperiod (1F), and is supplied only to a reset terminal of the shiftregister stage SRn which is the final stage of the second circuitsection 2 b.

As shown by (1) of FIG. 7, the gate scan is performed in a directionfrom the D2 side towards the D1 side in the period t1 and performed inthe direction from the D2 side towards the D1 side in the period t2.

Accordingly, the clock signals CKA13 and CKA23 charge/discharge thewires 10 b and 10 c only in the period t1 which is an operation periodof the first circuit section 2 a, and the clock signals CKB13 and CKB23charge/discharge the wires 10 e and 10 f only in the period t2 which isan operation period of the second circuit section 2 b. This greatlyreduces a loss of electricity associated with charging/discharging ofthe supply wires for supplying a drive signal, thereby further reducingwaveform deformation.

Further, a reduction in power consumption can be achieved since thefirst circuit section 2 a stops its operation in the period t2 and thesecond circuit section 2 b stops its operation in the period t1.

Further, the number of start pulse signals (here, gate start pulsesignals) declines since a shift pulse that is output from a shiftregister stage which is the final stage of one circuit section issupplied, as a shift pulse, to a shift register stage which is aninitial stage of another circuit section. This allows a reduction inelectricity for supplying the start pulse signals and a reduction in thenumber of wires for supplying the start pulse signals. The reduction inthe number of wires for supplying the start pulse signals allows areduction in area.

Example 5

FIG. 9 illustrates a configuration of a shift register circuit 3 of thepresent example.

The shift register circuit 3 of FIG. 9 includes a first circuit section3 a and a second circuit section 3 b.

The first circuit section 3 a has an identical configuration to thefirst circuit section 1 a of FIG. 1. To a set terminal SET of a shiftregister stage SR1 which is an initial stage of the first circuitsection 2 a, a gate start pulse signal GSP4 that is identical to thegate start pulse signal GSP1 is supplied. The second circuit section 3 bis different from the second circuit section 1 b of FIG. 1 in that aclock signal CKA14 described below is input instead of the gate startpulse signal GSP2.

Further, instead of the clock signals CKA1, CKA2, CKB1, and CKB2, andthe clear signal CLR of FIG. 1, clock signals (drive signals) CKA14,CKA24, CKB14, and CKB24, and the clear signal CLR3 are input,respectively.

As illustrated in FIG. 10, the clock signal CKA14 operates in the periodt1 of the clock signal CKA1 and operates at an active level in a periodof an initial clock pulse CKZ of the period t2, whereas, in a remainingperiod of the period t2, the clock signal CKA14 is in a rest period inwhich a non-active level is maintained. The clock signal CKA24 is asignal obtained by replacing the period t2 of the clock signal CKA2 witha rest period in which a non-active level is maintained. The clocksignals CKB14 and CKB24 are signals obtained by replacing the period t1of the clock signals CKB1 and CKB2 with a rest period in which anon-active level is maintained. The clear signal CLR3 is a signal whichbecomes an active level only in a final clock pulse period of 1 frameperiod (1F).

As illustrated in (1) of FIG. 9, the gate scan is performed in adirection from the D2 side towards the D1 side in the period t1 andperformed in the direction from the D2 side towards the D1 side in theperiod t2. In the period t1, the second circuit section 1 b stops itsoperation since the clock signals CKB14 and CKB24 are in a rest period.At the time of shift into the period t2, the clock pulse CKZ of theclock signal CKA14 is supplied, as a gate start pulse signal, to a setterminal SET of a shift register stage SRm+1 which is the initial stageof the second circuit section 3 b. In this way, the second circuitsection 3 b starts a shift operation.

In FIG. 9, a shift pulse may be shifted from the D1 side towards the D2side as follows. Specifically, the clock pulse CKZ of the clock signalCKA14 is supplied to a shift register stage SRn of the second circuitsection 3 b in a manner reverse to the order of cascade connection,instead of supplying a pulse of the clock signal CKA14 to the shiftregister stage SRm+1 which is the initial stage of the second circuitsection 3 b. In this case, the clear signal CLR3 is supplied to a resetterminal RESET of the shift register stage SRm+1 of the second circuitsection 3 b.

According to the arrangement of the present example, the clock signalsCKA14 and CKA24 charge/discharge the wires 10 b and 10 c only in theperiod t1 which is an operation period of the first circuit section 3 a,and the clock signals CKB14 and CKB24 charge/discharge the wires 10 eand 10 f only in the period t2 which is an operation period of thesecond circuit section 3 b. This greatly reduces a loss of electricityassociated with charging/discharging of the supply wires for supplying adrive signal, thereby further reducing waveform deformation.

Further, a reduction in power consumption can be achieved since thefirst circuit section 3 a stops its operation in the period t2 and thesecond circuit section 3 b stops its operation in the period t1.

Further, the number of start pulse signals (here, gate start pulsesignals) of the shift register circuit 1 declines since the last pulsebefore shift into a rest period out of pulses of a drive signal having arest period is input as a shift pulse of an i-th circuit section. Thisallows a reduction in electricity for supplying the start pulse signalsand a reduction in the number of wires for supplying the start pulsesignals. The reduction in the number of wires for supplying the startpulse signals allows a reduction in area.

Examples have been described.

There are variations in gate scan direction and in data signal supplydirection, as described above. The configuration of the liquid crystaldisplay device 11 may be appropriately modified as illustrated in (a)through (c) of FIG. 12 in accordance with these variations.

(a) of FIG. 12 illustrates an arrangement in which (i) the gate scan ofeach of the first through N-th circuit sections is performed in adirection from a side close to the source driver 16 provided in an upperpart of the display panel 12 towards a side far from the source driver16 or in a direction from the side far from the source driver 16 towardsthe side close to the source driver 16 and (ii) a data signal issupplied in a direction from the side close to the source driver 16towards the side far from the source driver 16.

(b) of FIG. 12 illustrates an arrangement in which (i) the gate scan ofeach of the first through N-th circuit sections is performed in adirection from a side close to the source driver 16 provided in a lowerpart of the display panel 12 towards a side far from the source driver16 or in a direction from the side far from the source driver 16 towardsthe side close to the source driver 16 and (ii) a data signal issupplied in a direction from the side close to the source driver 16towards the side far from the source driver 16.

(c) of FIG. 12 illustrates an arrangement in which (i) a screen isdivided into a first screen, which is an upper screen, and a secondscreen, which is a lower screen, (ii) the first through N-th circuitsections are allocated to the upper screen (first screen) and the lowerscreen (second screen), and (iii) a control board 14 a, a flexibleprinted circuit board 13 a, a source driver (first data signal linedriving circuit) 16 a, each of which is for the upper screen and acontrol board 14 b, a flexible printed circuit board 13 b, a sourcedriver (second data signal line driving circuit) 16 b, each of which isfor the lower screen are provided. In this case, the gate scan and thedata signal supply may be performed in a direction from a side close toa corresponding source driver to a side far from the correspondingsource driver. The gate scan may be performed in any of the directionsboth in the upper and lower screens.

Further, the display device may be another display device such as an ELdisplay device.

As described above, a shift register circuit of the present inventionincludes: first through N-th circuit sections (N is an integer equal toor larger than 2) in each of which a plurality of shift register stagesare connected in cascade; and supply wires, each of the first throughN-th circuit sections receiving a drive signal for driving the pluralityof shift register stages via a supply wire exclusive for said each ofthe first through N-th circuit sections out of the supply wires.

According to the invention, the number of intersections of each of thesupply wires for supplying a drive signal and another wire greatlydeclines. This makes it possible to greatly reduce the capacitances ofcross capacitors per supply wire for supplying a drive signal. Further,the number of shift register stages connected to each of the supplywires for supplying a drive signal greatly declines. This allows a greatreduction in sum of parasitic capacitors in connection parts with theshift register stages. Accordingly, a drive signal that is supplied froma drive signal source to each of the supply wires for supplying a drivesignal can have a waveform with smaller deformation, and therefore awaveform of an output signal from each of the shift register stages canhave a waveform with smaller deformation, as compared with aconventional art. Consequently, it is possible to increase a chargingratio of a load without increasing a voltage range of the drive signalsource nor increasing a transistor size (channel width), therebyincreasing an operation margin of the shift register stages.

It is thus possible to provide a shift register circuit that makes itpossible to secure a sufficient operation margin.

The shift register circuit of the present invention is arranged suchthat a direction along a shift direction is a first direction and adirection perpendicular to the first direction on a surface on which theshift register circuit is provided is a second direction, the firstthrough N-th circuit sections are aligned in the first direction, thenumber of shift register stages is determined for each of the firstthrough N-th circuit sections, and each of the supply wires whichcorresponds to one of the first through N-th circuit sections isprovided in a first region that is located closer, than thecorresponding one of the first through N-th circuit sections, to apredetermined side of the second direction, which is one side of thesecond direction and which is common to all of the first through N-thcircuit sections, so as to extend from a predetermined side of the firstdirection, which is one side of the first direction and which is commonto all of the first through N-th circuit sections, towards thecorresponding one of the first through N-th circuit sections.

According to the invention, it is possible to provide a shift registercircuit that makes it possible to secure a sufficient operation marginin a case where a drive signal source is provided only on thepredetermined side of the first direction.

The shift register circuit of the present invention is arranged suchthat each of the supply wires has a main wire that extends in the firstdirection and branch wires each of which branches off from the main wiretowards a corresponding one of the first through N-th circuit sectionsso as to be connected to the corresponding one of the first through N-thcircuit sections.

According to the invention, it is possible to greatly reduce thecapacitances of cross capacitors formed as a result of presence of themain wire and the branch wires.

The shift register circuit of the present invention is arranged suchthat out of the supply wires, a supply wire corresponding to one of thefirst through N-th circuit sections which one is farther from thepredetermined side of the first direction when viewed from a directionalong the first direction has a main wire that is closer to thepredetermined side of the second direction in the first region.

According to the invention, it is possible to minimize the number ofparts where a cross capacitor is formed, in a case where a drive signalsource is provided only on the predetermined side of the firstdirection.

The shift register circuit of the present invention is arranged suchthat a direction along a shift direction is a first direction and adirection perpendicular to the first direction on a surface on which theshift register circuit is provided is a second direction, each of thesupply wires which corresponds to one of the first through N-th circuitsections is provided in a first region that is located closer, than thecorresponding one of the first through N-th circuit sections, to apredetermined side of the second direction, which is one side of thesecond direction and which is common to for all of the first throughN-th circuit sections, so that, out of the supply wires, (i) a supplywire corresponding to one of the first through N-th circuit sectionswhich one is provided closer to a predetermined side of the firstdirection which is one side of the first direction extends from thepredetermined side of the first direction towards the corresponding oneof the first through N-th circuit sections and (ii) a supply wirecorresponding to one of the first through N-th circuit sections whichone is provided closer to an opposite side to the predetermined side ofthe first direction extends from the opposite side to the predeterminedside of the first direction towards the corresponding one of the firstthrough N-th circuit sections.

According to the invention, a balance can be achieved between lengths ofsupply wires on the predetermined side of the first direction of theshift register circuit and lengths of supply wires on the opposite sideto the predetermined side of the first direction. Accordingly, adifference is unlikely occur in deformation of a waveform of a drivesignal, and therefore a difference is unlikely occur in deformation of awaveform of an output signal of each of the shift register stages.

The shift register circuit of the present invention is arranged suchthat each of the supply wires has a main wire that extends in the firstdirection and branch wires each of which branches off from the main wiretowards a corresponding one of the first through N-th circuit sectionsso as to be connected to the corresponding one of the first through N-thcircuit sections.

According to the invention, it is possible to greatly reduce the numberof cross capacitors formed as a result of presence of the main wire andthe branch wires.

The shift register circuit of the present invention is arranged suchthat the drive signal for one of the first through N-th circuit sectionshas a rest period within an operation period of another one of the firstthrough N-th circuit sections.

According to the invention, the presence of the rest period reduces aloss of electricity associated with charging/discharging in the supplywires for supplying a drive signal, thereby further reducing waveformdeformation. Further, a reduction in power consumption can be achievedsince an operation of a corresponding one of the first through N-thcircuit sections is stopped.

The shift register circuit of the present invention is arranged suchthat out of pulses of the drive signal having the rest period, a lastpulse before shift into the rest period is input as a shift pulse forone of the first through N-th circuit sections.

According to the invention, out of pulses of a drive signal having arest period, a last pulse before shift into the rest period is input asa shift pulse of one of the first through N-th circuit sections.Accordingly, the number of start pulses of the shift register circuitdeclines. This allows a reduction in electricity for supplying the startpulse signals and a reduction in the number of wires for supplying thestart pulse signals. The reduction in the number of wires for supplyingthe start pulse signals allows a reduction in area.

The shift register circuit of the present invention is arranged suchthat a shift pulse that is output from a shift register stage which is afinal stage of one of the first through N-th circuit sections issupplied, as a shift pulse, to a shift register stage which is aninitial stage of another one of the first through N-th circuit sections.

According to the invention, a shift pulse that is output from a shiftregister stage which is a final stage of one of the first through N-thcircuit sections is supplied, as a shift pulse, to a shift registerstage which is an initial stage of another one of the first through N-thcircuit sections. Accordingly, the number of start pulse signalsdeclines. This allows a reduction in electricity for supplying the startpulse signals and a reduction in the number of wires for supplying thestart pulse signals. The reduction in the number of wires for supplyingthe start pulse signals allows a reduction in area.

The shift register circuit of the present invention is arranged suchthat the shift register circuit is formed from at least one of amorphoussilicon, polycrystalline silicon, CG silicon, microcrystalline silicon,and amorphous oxide semiconductor.

According to the invention, the shift register circuit can bemonolithically built into a device formed with the use of such amaterial.

A display device of the present invention includes the shift registercircuit.

According to the invention, it is possible to provide a display devicewhich allows a large operation margin and high-quality display.

The display device of the present invention further includes: a screenthat is divided into a first screen and a second screen, each of thefirst through N-th circuit sections being allocated to the first screenor the second screen; a first data signal line driving circuit forsupplying a data signal corresponding to the first screen; and a seconddata signal line driving circuit for supplying a data signalcorresponding to the second screen.

According to the invention, the upper and lower screens thus divided canbe driven by the first through N-th circuit sections, each of which isallocated to the upper screen or the lower screen, with the use of adrive signal having a long cycle. This makes it possible to secure along selection period of a picture element. Consequently, highresolution and high-speed display can be achieved well.

A method of the present invention for driving a shift register circuitwhich includes first through N-th circuit sections (N is an integerequal to or larger than 2) in each of which a plurality of shiftregister stages are connected in cascade, includes the step ofsupplying, to each of the first through N-th circuit sections, a drivesignal for driving the plurality of shift register stages via a supplywire exclusive for said each of the first through N-th circuit sections.

According to the invention, it is possible to provide a method fordriving a shift register circuit that makes it possible to secure asufficient operation margin.

The present invention is not limited to the description of theembodiments above, but may be altered by a skilled person within thescope of the claims. An embodiment based on a proper combination oftechnical means disclosed in different embodiments is encompassed in thetechnical scope of the present invention.

INDUSTRIAL APPLICABILITY

The present invention is suitably applicable to an active matrix displaydevice.

REFERENCE SIGNS LIST

-   1: Shift register circuit-   1 a: First circuit section (i-th circuit section)-   1 b: Second circuit section (i-th circuit section)-   2 a: First circuit section (i-th circuit section)-   2 b: Second circuit section (i-th circuit section)-   3 a: First circuit section (i-th circuit section)-   3 b: Second circuit section (i-th circuit section)-   10 b: Wire (supply wire)-   10 c: Wire (supply wire)-   10 e: Wire (supply wire)-   10 f: Wire (supply wire)-   10 b(1): Main wire-   10 c(1): Main wire-   10 e(1): Main wire-   10 f(1): Main wire-   10 b(2): Branch wire-   10 c(2): Branch wire-   10 e(2): Branch wire-   10 f(2): Branch wire-   11: Liquid crystal display device (display device)-   12: Display panel-   12 a: Active region-   12 b(1): Region (first region)-   16 a: Source driver (first data signal line driving circuit)-   16 b: Source driver (second data signal line driving circuit)-   SRk: Stage (shift register stage)-   CKA1, CKA2, CKB1, CKB2: Clock signal (drive signal)-   CKA12, CKA22, CKB12, CKB22: Clock signal (drive signal)-   CKA13, CKA23, CKB13, CKB23: Clock signal (drive signal)-   CKA14, CKA24, CKB14, CKB24: Clock signal (drive signal)-   D: Direction (first direction)-   D1: (Side) (predetermined side of first direction)-   D2: (Side) (opposite side to a predetermined side of first    direction)-   E: Direction (second direction)-   E1: (Side) (predetermined side of second direction)

1. A shift register circuit comprising: first through N-th circuitsections (N is an integer equal to or larger than 2) in each of which aplurality of shift register stages are connected in cascade; and supplywires, each of the first through N-th circuit sections receiving a drivesignal for driving the plurality of shift register stages via a supplywire exclusive for said each of the first through N-th circuit sectionsout of the supply wires.
 2. The shift register circuit according toclaim 1, wherein: a direction along a shift direction is a firstdirection and a direction perpendicular to the first direction on asurface on which the shift register circuit is provided is a seconddirection, the first through N-th circuit sections are aligned in thefirst direction, the number of shift register stages is determined foreach of the first through N-th circuit sections, and each of the supplywires which corresponds to one of the first through N-th circuitsections is provided in a first region that is located closer, than thecorresponding one of the first through N-th circuit sections, to apredetermined side of the second direction, which is one side of thesecond direction and which is common to all of the first through N-thcircuit sections, so as to extend from a predetermined side of the firstdirection, which is one side of the first direction and which is commonto all of the first through N-th circuit sections, towards thecorresponding one of the first through N-th circuit sections.
 3. Theshift register circuit according to claim 2, wherein: each of the supplywires has a main wire that extends in the first direction and branchwires each of which branches off from the main wire towards acorresponding one of the first through N-th circuit sections so as to beconnected to the corresponding one of the first through N-th circuitsections.
 4. The shift register circuit according to claim 3, wherein:out of the supply wires, a supply wire corresponding to one of the firstthrough N-th circuit sections which one is farther from thepredetermined side of the first direction when viewed from a directionalong the first direction has a main wire that is closer to thepredetermined side of the second direction in the first region.
 5. Theshift register circuit according to claim 1, wherein: a direction alonga shift direction is a first direction and a direction perpendicular tothe first direction on a surface on which the shift register circuit isprovided is a second direction, each of the supply wires whichcorresponds to one of the first through N-th circuit sections isprovided in a first region that is located closer, than thecorresponding one of the first through N-th circuit sections, to apredetermined side of the second direction, which is one side of thesecond direction and which is common to all of the first through N-thcircuit sections, so that, out of the supply wires, (i) a supply wirecorresponding to one of the first through N-th circuit sections whichone is provided closer to a predetermined side of the first directionwhich is one side of the first direction extends from the predeterminedside of the first direction towards the corresponding one of the firstthrough N-th circuit sections and (ii) a supply wire corresponding toone of the first through N-th circuit sections which one is providedcloser to an opposite side to the predetermined side of the firstdirection extends from the opposite side to the predetermined side ofthe first direction towards the corresponding one of the first throughN-th circuit sections.
 6. The shift register circuit according to claim5, wherein: each of the supply wires has a main wire that extends in thefirst direction and branch wires each of which branches off from themain wire towards a corresponding one of the first through N-th circuitsections so as to be connected to the corresponding one of the firstthrough N-th circuit sections.
 7. The shift register circuit accordingto claim 1, wherein: the drive signal for one of the first through N-thcircuit sections has a rest period within an operation period of anotherone of the first through N-th circuit sections.
 8. The shift registercircuit according to claim 7, wherein: out of pulses of the drive signalhaving the rest period, a last pulse before shift into the rest periodis input as a shift pulse for one of the first through N-th circuitsections.
 9. The shift register circuit according to claim 1, wherein: ashift pulse that is output from a shift register stage which is a finalstage of one of the first through N-th circuit sections is supplied, asa shift pulse, to a shift register stage which is an initial stage ofanother one of the first through N-th circuit sections.
 10. The shiftregister circuit according to claim 1, wherein: the shift registercircuit is formed from at least one of amorphous silicon,polycrystalline silicon, CG silicon, microcrystalline silicon, andamorphous oxide semiconductor.
 11. A display device comprising a shiftregister circuit as set forth in claim
 1. 12. A display device accordingto claim 11, further comprising: a screen that is divided into a firstscreen and a second screen, each of the first through N-th circuitsections being allocated to the first screen or the second screen; afirst data signal line driving circuit for supplying a data signalcorresponding to the first screen; and a second data signal line drivingcircuit for supplying a data signal corresponding to the second screen.13. A method for driving a shift register circuit which includes firstthrough N-th circuit sections (N is an integer equal to or larger than2) in each of which a plurality of shift register stages are connectedin cascade, the method comprising the step of supplying, to each of thefirst through N-th circuit sections, a drive signal for driving theplurality of shift register stages via a supply wire exclusive for saideach of the first through N-th circuit sections.